1. Technical Field
The disclosure relates generally to semiconductor wafer metrology, and more particularly, to a system for evaluating a semiconductor wafer and detecting pitch walking and/or epitaxial merge.
2. Background Art
Integrated circuit (IC) chips are formed on semiconductor wafers at increasingly smaller scale. In current technology nodes, such as 7, 10 and 14 nanometer technologies, transistor devices are constructed as three-dimensional (3D) fin field effect transistor (FINFET) structures. As shown in the scanning electron microscope (SEM) image of FIG. 1, the fins of the FINFETS are expected to be constructed as repeating, equally spaced, vertical structures on the wafer. Equally spaced gates are formed as repeating vertical structures that overlay the fins in an orthogonal direction.
A challenge in constructing the repeating structures such as fins and gates at these advanced technology nodes is that variability in pitch spacing between the structures and pitch walking can occur during the formation of the structures using current sidewall image transfer (SIT) photolithography techniques. “Pitch walking” is a condition, as shown in the SEM image of FIG. 2, in which expected, periodic structures, e.g., fins as shown, are constructed with unequal spacing and different periodicities. In the example shown, the fins are paired with members of each pair closer together than they are to an adjacent pair, resulting in a non-uniform pitch across all of the structures. In some instances, adjacent fins and/or gates may merge into a single structure. Pitch walking can occur relative to fins and at the gate patterning level, and is detrimental to device yield. In addition to fins and gates, in subsequent processing, epitaxial films are deposited on the fins. Avoiding merging of epitaxially grown structures (“epi merge”) is a key metric for device performance targets. Since SIT photolithography techniques will be implemented in the above-identified technology nodes, pitch tolerance will be important for accurately constructing devices, e.g., landing contacts on gates. In this regard, pitch walking tolerance requirements are anticipated to be +/−1 nanometer (nm).
Tolerances of +/−1 nm, however, are below the sensitivity of existing metrology techniques, and so the ability to detect pitch walking has become more difficult as the critical dimensions (CDs) and pitch spacing shrink. In particular, traditional in-line measurement techniques (e.g., critical dimension scanning electron microscope (CDSEM)) do not have the precision and the capability to determine the pitch walking at the requisite size, e.g., on the order of 1 nm. CDSEM techniques are also difficult to implement because the structures that exist at such small CDs exhibit line edge roughness that complicates measurements. Optical reflectometry-based scatterometric techniques are also problematic because they are model based, use data that can be convoluted by any underlying topography and films, and are generally unproven.